Physical vapor deposition process for semiconductor interconnection structures
US11018055B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2019 |
| Grant date | May 25, 2021 |
| Priority date | — |
| Expiry date | Dec 20, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53238
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides methods for forming a conductive fill material (e.g., a conductive feature) by a physical vapor deposition (PVD) process. In one embodiment, a method of forming a conductive fill material on a substrate includes maintaining a first substrate temperature at a first range for a first period of time while forming a pre-layer of a conductive fill material on a substrate, providing a thermal energy to the substrate to maintain the substrate at a second substrate temperature at a second range for a second period of time, wherein the second substrate temperature is higher than the first substrate temperature, and continuously providing the thermal energy to the substrate to maintain the substrate a third substrate temperature at a third range for a third period of time to form a bulk layer of the conductive fill material on the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.