Semiconductor device having a passivation layer
US11018100B2 · kind B2 · utility
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3References
20Claims
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Assignee
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Key dates
| Filing date | May 13, 2019 |
| Grant date | May 25, 2021 |
| Priority date | — |
| Expiry date | May 30, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/381
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a conductive pad over an interconnect structure, wherein the conductive pad is electrically connected to an active device. The semiconductor device includes a dielectric layer over the conductive pad, wherein the dielectric layer comprises silicon oxide. The semiconductor device includes a first passivation layer directly over the dielectric layer, wherein the first passivation layer comprises silicon oxide. The semiconductor device includes a second passivation layer directly over the first passivation layer, wherein the second passivation layer comprises silicon nitride.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.