Embedded memory device and method for embedding memory device in a substrate
US11018124B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 31, 2018 |
| Grant date | May 25, 2021 |
| Priority date | — |
| Expiry date | Aug 31, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1437
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A system and method of providing high bandwidth and low latency memory architecture solutions for next generation processors is disclosed. The package contains a substrate, a memory device embedded in the substrate via EMIB processes and a processor disposed on the substrate partially over the embedded memory device. The I/O pads of the processor and memory device are vertically aligned to minimize the distance therebetween and electrically connected through EMIB uvias. An additional memory device is disposed on the substrate partially over the embedded memory device or on the processor. I/O signals are routed using a redistribution layer on the embedded memory device or an organic VHD redistribution layer formed over the embedded memory device when the additional memory device is laterally adjacent to the processor and the I/O pads of the processor and additional memory device are vertically aligned when the additional memory device is on the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.