Inventor · Chandler, AZ, US

Andrew Collins

26Patents
3h-index
28Co-inventors
59Inventor score

Filing activity: Dec 20, 2011 → Jun 21, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US10847467B2 Power-delivery methods for embedded multi-die interconnect bridges and methods of assembling same Electricity 16 Active
US11270942B2 Pitch translation architecture for semiconductor package including embedded interconnect bridge Electricity 3 Active
US10490503B2 Power-delivery methods for embedded multi-die interconnect bridges and methods of assembling same Electricity 3 Active
US11705398B2 Pitch translation architecture for semiconductor package including embedded interconnect bridge Electricity 2 Active
US8913364B2 Decoupling arrangement Electricity 2 Active
US10643945B2 Pitch translation architecture for semiconductor package including embedded interconnect bridge Electricity 2 Active
US9225164B2 Decoupling arrangement Electricity 1 Active
US10651117B2 Low-inductance current paths for on-package power distributions and methods of assembling same Electricity 1 Active
US11018124B2 Embedded memory device and method for embedding memory device in a substrate Electricity 1 Active
US12051647B2 Pitch translation architecture for semiconductor package including embedded interconnect bridge Electricity 1 Active
US11610862B2 Semiconductor packages with chiplets coupled to a memory device Electricity 0 Active
US11195805B2 Capacitor die embedded in package substrate for providing capacitance to surface mounted die Electricity 0 Active
US11387187B2 Embedded very high density (VHD) layer Electricity 0 Active
US12046568B2 Capacitor die embedded in package substrate for providing capacitance to surface mounted die Electricity 0 Active
US11728294B2 Capacitor die embedded in package substrate for providing capacitance to surface mounted die Electricity 0 Active
US11621223B2 Interconnect hub for dies Electricity 0 Active
US11705390B2 Variable in-plane signal to ground reference configurations Electricity 0 Active
US11569173B2 Bridge hub tiling architecture Electricity 0 Active
US11222837B2 Low-inductance current paths for on-package power distributions and methods of assembling same Electricity 0 Active
US12388019B2 Pitch translation architecture for semiconductor package including embedded interconnect bridge Electricity 0 Active
US12205924B2 Semiconductor packages with chiplets coupled to a memory device Electricity 0 Active
US11456281B2 Architecture and processes to enable high capacity memory packages through memory die stacking Electricity 0 Active
US12347780B2 Integrated circuit package with flipped high bandwidth memory device Electricity 0 Active
US11562993B2 Embedded memory device and method for embedding memory device in a substrate Electricity 0 Active
US11462521B2 Multilevel die complex with integrated discrete passive components Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.