Vertically stacked semiconductor devices having vertical channel transistors

US11018235B2 · kind B2 · utility

Assignees

• IMEC VZW · BE
• VRIJE UNIVERSITEIT BRUSSEL · BE

Inventors

• Trong Huynh Bao · Leuven, BE
• Anabela Veloso · Leuven, BE
• Julien Ryckaert · Schaerbeek - Schaarbeek, BE

Key dates

• Filing date: Nov 11, 2016
• Grant date: May 25, 2021
• Expiry date: Nov 11, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6729
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

The disclosed technology generally relates to semiconductor devices, and more particularly to semiconductor devices having a stacked arrangement, and further relates to methods of fabricating such devices. In one aspect, a semiconductor device comprises a first memory device and a second memory device formed over a substrate and at least partly stacked in a vertical direction. Each of the first and second memory devices has a plurality of vertical transistors, wherein each vertical transistor has a vertical channel extending in the vertical direction.