Selective internal gate structure for ferroelectric semiconductor devices
US11018256B2 · kind B2 · utility
3Cited by
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20Claims
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Assignee
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Key dates
| Filing date | Aug 23, 2019 |
| Grant date | May 25, 2021 |
| Priority date | — |
| Expiry date | Aug 23, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a semiconductor device including a substrate and first and second spacers on the substrate. The semiconductor device also includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers; an internal gate formed on the first and second portions of the gate dielectric layer; a ferroelectric dielectric layer formed on the internal gate and in contact with the gate dielectric layer; and a gate electrode on the ferroelectric dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.