Systems and methods to zero a tile register pair
US11023235B2 · kind B2 · utility
19Cited by
25References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2017 |
| Grant date | Jun 1, 2021 |
| Priority date | — |
| Expiry date | Jan 22, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3877
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments detailed herein relate to systems and methods to zero a tile register pair. In one example, a processor includes decode circuitry to decode a matrix pair zeroing instruction having fields for an opcode and an identifier to identify a destination matrix having a PAIR parameter equal to TRUE; and execution circuitry to execute the decoded matrix pair zeroing instruction to zero every element of a left matrix and a right matrix of the identified destination matrix.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.