Techniques for supporting erasure coding with flash memory controller
US11023315B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 3, 2019 |
| Grant date | Jun 1, 2021 |
| Priority date | — |
| Expiry date | Feb 5, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7211
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Processing functions are offloaded to a memory controller for nonvolatile memory by a host in connection with write data. The nonvolatile memory executes these functions, producing processed data that must be written into memory; for example, the offloaded functions can include erasure coding, with the nonvolatile memory controller generating redundancy information that must be written into memory. The memory controller holds this information in internal RAM and then later writes this information into nonvolatile memory according to dynamically determined write time and/or destinations selected by the host, so as to not collide with host data access requests. In one embodiment, the memory is NAND flash memory and the memory controller is a cooperative memory controller that permits the host to schedule concurrent operations in respective, configurable virtual block devices which have been configured by the host out of a pool of structural flash memory structures managed by the memory controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.