Patent · US Active

Technologies for providing multiple levels of error correction

US11023320B2 · kind B2 · utility

1Cited by

5References

16Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Wei Wu · Portland, US
Rajesh Sundaram · Folsom, US
Chetan Chauhan · Folsom, US
Jawad B. Khan · Cornelius, US
Shigeki Tomishima · Portland, US
Srikanth Srinivasan · Bengaluru, IN

Key dates

Filing date	Apr 4, 2019
Grant date	Jun 1, 2021
Priority date	—
Expiry date	Apr 4, 2039

Classification

Technology area (CPC G)Physics
CPC primaryG06F11/1048
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Technologies for providing multiple levels of error correction include a memory that includes media access circuitry coupled to a memory media. The media access circuitry is to read data from the memory media. Additionally, the media access circuitry is to perform, with an error correction logic unit located in the media access circuitry, error correction on the read data to produce error-corrected data.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.