Memory system having a plurality of memory chips and method for controlling power supplied to the memory chips
US11023370B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 25, 2019 |
| Grant date | Jun 1, 2021 |
| Priority date | — |
| Expiry date | Feb 25, 2039 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes a non-volatile memory having a plurality of memory chips, a plurality of switches provided for each of the memory chips for switching on and off supply of power to the corresponding memory chip, and a memory controller configured to control the switches and data access to the non-volatile memory. The memory controller is further configured to determine whether there is a first memory chip among the plurality of memory chips that has no data item stored therein with an elapsed time from a most recent access thereof that is less than a threshold value, and if so, turn off the supply of power to the first memory chip while maintaining the supply of power to the plurality of memory chips other than the first memory chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.