Data cache with hybrid writeback and writethrough
US11023375B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 21, 2020 |
| Grant date | Jun 1, 2021 |
| Priority date | — |
| Expiry date | Feb 21, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described is a data cache implementing hybrid writebacks and writethroughs. A processing system includes a memory, a memory controller, and a processor. The processor includes a data cache including cache lines, a write buffer, and a store queue. The store queue writes data to a hit cache line and an allocated entry in the write buffer when the hit cache line is initially in at least a shared coherence state, resulting in the hit cache line being in a shared coherence state with data and the allocated entry being in a modified coherence state with data. The write buffer requests and the memory controller upgrades the hit cache line to a modified coherence state with data based on tracked coherence states. The write buffer retires the data upon upgrade. The data cache writebacks the data to memory for a defined event.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.