Systems, methods, and apparatuses utilizing CPU storage with a memory reference
US11023382B2 · kind B2 · utility
13Cited by
1References
9Claims
0Family size
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Key dates
| Filing date | Dec 22, 2017 |
| Grant date | Jun 1, 2021 |
| Priority date | — |
| Expiry date | Dec 26, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/454
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Implementations of using tiles for caching are detailed In some implementations, an instruction execution circuitry executes one or more instructions, a register state cache coupled to the instruction execution circuitry holds thread register state in a plurality of registers, and backing storage pointer storage stores a backing storage pointer, wherein the backing storage pointer is to reference a state backing storage area in external memory to store the thread register state stored in the register state cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.