Pseudo-asynchronous digital circuit design
US11023632B2 · kind B2 · utility
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11References
23Claims
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Key dates
| Filing date | Jun 29, 2017 |
| Grant date | Jun 1, 2021 |
| Priority date | — |
| Expiry date | Aug 8, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/034
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A logic element includes a logic block, a supply voltage input, switchable power gates and a gate selector. The logic block implements a logic function on input data to obtain at least one output data signal. The switchable power gates transfer a supply voltage from the supply voltage input to the logic block in accordance with respective gate control signals. At least two of the power gates have different respective electrical properties. The gate selector switches on differing ones of the power gates in accordance with gate selection data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.