Package structure and method of manufacturing the same
US11024616B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 2019 |
| Grant date | Jun 1, 2021 |
| Priority date | — |
| Expiry date | May 16, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a package structure including at least two chips, an interposer, a first encapsulant, and a second encapsulant. The at least two chips are disposed side by side and bonded to the interposer by a plurality of connectors. The first encapsulant is disposed on the interposer and filling in a gap between the at least two chips. The second encapsulant encapsulates the plurality of connectors and surrounding the at least two chips, wherein the second encapsulant is in contact with the first encapsulant sandwiched between the at least two chips, and a material of the second encapsulant has a coefficient of thermal expansion (CTE) larger than a CTE of a material of the first encapsulant. A method of manufacturing a package structure is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.