Integrated circuits and processes for protection of standard cell performance from context effects
US11024620B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2018 |
| Grant date | Jun 1, 2021 |
| Priority date | — |
| Expiry date | Aug 2, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/931
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Integrated circuit (5) includes substrate (10) with surface (20) and structure (30) including base levels (45.i, 45.(i+1)), terminating cells (48, 49), and block (40) of standard cells arranged in rows (42.i, 42.(i+1)), and another type of block (60) outside block (40). Standard cells at at least two edges of block (40) have the following protections: (1) block (60) has strip of separation (41.j) having at least a minimum width from the edges of block (40), and protected by one of the following: (2) terminating cells (48, 49) reduce context effect and some terminating cells (48) are placed at at least one end of rows (42.i, 42.(i+1)) of standard cells within first-named block (40), and (3) the terminating cells (48, 49) reduce context effect and some terminating cells (49) are at one end of a column of standard cells within block (40). Other structures, devices, and processes are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.