Diffused field-effect transistor and method of fabricating same
US11024722B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 2020 |
| Grant date | Jun 1, 2021 |
| Priority date | — |
| Expiry date | Mar 25, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
Abstract
A diffused field-effect transistor (FET) and a method of fabricating same are disclosed. The diffused FET is dually optimized in voltage resistance by incorporating both a trench isolation structure and a thick second oxide layer and thus has a more significantly improved breakdown voltage. With the thick second oxide layer ensuring suitable voltage resistance of the transistor device, its on-resistance can be reduced either by reducing the size of the trench isolation structure or increasing an ion dopant concentration of a drift region. As such, a good tradeoff between voltage resistance and on-resistance is achievable.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.