Three dimensional vertically structured electronic devices

US11024734B2 · kind B2 · utility

Assignee

• Lawrence Livermore National Security, LLC · US

Inventors

• Adam Conway · Livermore, US
• Sara Elizabeth Harrison · Livermore, US
• Rebecca J. Nikolic · Oakland, US
• Qinghui Shao · Fremont, US
• Lars Voss · Livermore, US

Key dates

• Filing date: Jan 4, 2017
• Grant date: Jun 1, 2021
• Expiry date: Nov 12, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/8503

Abstract

In one embodiment, a method of forming a vertical transistor includes forming a layer comprising a semiconductor material above a substrate, defining three dimensional (3D) structures in the layer, forming a second region in at least one vertical sidewall of each 3D structure, and forming an isolation region between the 3D structures. In another embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate comprising a semiconductor material, an array of 3D structures above the substrate, and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, the second region including a portion of at least one vertical sidewall of the 3D structure.