Methods and apparatus for decoding video using re-ordered motion vector buffer
US11025934B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2014 |
| Grant date | Jun 1, 2021 |
| Priority date | — |
| Expiry date | Dec 14, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/44
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A host processor, such as a central processing unit (CPU), programmed to execute a software driver that causes the host processor to generate a motion compensation command for a plurality of cores of a massively parallel processor, such as a graphics processing unit (GPU), to provide motion compensation for encoded video. The motion compensation command for the plurality of cores of the massively parallel processor contains executable instructions for processing a plurality of motion vectors grouped by a plurality of prediction modes from a re-ordered motion vector buffer by the plurality of cores of the massively parallel processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.