On-demand multi-tiered hang buster for SMT microprocessor
US11030018B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2017 |
| Grant date | Jun 8, 2021 |
| Priority date | — |
| Expiry date | Oct 8, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments include systems, methods, and computer program products for using a multi-tier hang buster for detecting and breaking out of hang conditions in a processor. One method includes determining a plurality of actions available at each of a plurality of tiers used for breaking out of the hang condition in the processor. The method also includes, after detecting the hang condition on a first thread of the processor, performing one or more actions available at a first tier of the plurality of tiers to break out of the hang condition. The method further includes, after performing the one or more actions at the first tier and determining that the hang condition is still present, performing one or more actions available at one or more second tiers of the plurality of tiers to break out of the hang condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.