Inventor · Austin, TX, US

Cliff Kucharski

23Patents
3h-index
27Co-inventors
55Inventor score

Filing activity: May 7, 2015 → Dec 5, 2022

Most-cited inventions

PatentTitleAreaCited byStatus
US9639418B2 Parity protection of a register Physics 4 Active
US9740620B2 Distributed history buffer flush and restore handling in a parallel slice design Physics 4 Active
US10073699B2 Processing instructions in parallel with waw hazards and via a distributed history buffer in a microprocessor having a multi-execution slice architecture Physics 4 Active
US9747217B2 Distributed history buffer flush and restore handling in a parallel slice design Physics 3 Active
US10949205B2 Implementation of execution compression of instructions in slice target register file mapper Physics 1 Active
US11144364B2 Supporting speculative microprocessor instruction execution Physics 1 Active
US10613868B2 Variable latency pipe for interleaving instruction tags in a microprocessor Physics 0 Active
US11561794B2 Evicting and restoring information using a single port of a logical register mapper and history buffer in a microprocessor comprising multiple main register file entries mapped to one accumulator register file entry Physics 0 Active
US10282205B2 Method and apparatus for execution of threads on processing slices using a history buffer for restoring architected register data via issued instructions Physics 0 Active
US10318356B2 Operation of a multi-slice processor implementing a hardware level transfer of an execution thread Physics 0 Active
US10255071B2 Method and apparatus for managing a speculative transaction in a processing unit Physics 0 Active
US11030018B2 On-demand multi-tiered hang buster for SMT microprocessor Physics 0 Active
US11188332B2 System and handling of register data in processors Physics 0 Active
US10241790B2 Operation of a multi-slice processor with reduced flush and restore latency Physics 0 Active
US10248421B2 Operation of a multi-slice processor with reduced flush and restore latency Physics 0 Active
US10289415B2 Method and apparatus for execution of threads on processing slices using a history buffer for recording architected register data Physics 0 Active
US11194578B2 Fused overloaded register file read to enable 2-cycle move from condition register instruction in a microprocessor Physics 0 Active
US10649779B2 Variable latency pipe for interleaving instruction tags in a microprocessor Physics 0 Active
US11768684B2 Compaction of architected registers in a simultaneous multithreading processor Physics 0 Active
US11138050B2 Operation of a multi-slice processor implementing a hardware level transfer of an execution thread Physics 0 Active
US10489253B2 On-demand GPR ECC error detection and scrubbing for a multi-slice microprocessor Physics 0 Active
US11941398B1 Fast mapper restore for flush in processor Physics 0 Active
US11093282B2 Register file write using pointers Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.