Processing system with interspersed processors DMA-FIFO
US11030023B2 · kind B2 · utility
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17References
20Claims
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Key dates
| Filing date | Jul 25, 2016 |
| Grant date | Jun 8, 2021 |
| Priority date | — |
| Expiry date | Jan 6, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of a multi-processor array are disclosed that may include a plurality of processors, local memories, configurable communication elements, and direct memory access (DMA) engines, and a DMA controller. Each processor may be coupled to one of the local memories, and the plurality of processors, local memories, and configurable communication elements may be coupled together in an interspersed arrangement. The DMA controller may be configured to control the operation of the plurality of DMA engines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.