Keith M. Bindloss
19Patents
5h-index
27Co-inventors
66Inventor score
Filing activity: Jul 26, 1993 → Jan 3, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5544311A | On-chip debug port | Physics | 137 | Expired |
| US5778241A | Space vector data path | Physics | 87 | Expired |
| US6684319B1 | System for efficient operation of a very long instruction word digital signal processor | Physics | 34 | Expired |
| US9430369B2 | Memory-network processor with programmable optimizations | Emerging Cross-Sectional Technologies | 12 | Active |
| US5479626A | Signal processor contexts with elemental and reserved group addressing | Physics | 10 | Expired |
| US9424213B2 | Processing system with interspersed processors DMA-FIFO | Emerging Cross-Sectional Technologies | 2 | Active |
| US7266811B2 | Methods, systems, and computer program products for translating machine code associated with a first processor for execution on a second processor | Physics | 2 | Expired |
| US5586284A | Triple register RISC digital signal processor | Physics | 1 | Expired |
| US10747709B2 | Memory network processor | Emerging Cross-Sectional Technologies | 1 | Active |
| US11829320B2 | Memory network processor | Emerging Cross-Sectional Technologies | 0 | Active |
| US11900124B2 | Memory-network processor with programmable optimizations | Emerging Cross-Sectional Technologies | 0 | Active |
| US11016779B2 | Memory-network processor with programmable optimizations | Emerging Cross-Sectional Technologies | 0 | Active |
| US12197970B2 | Processing system with interspersed processors DMA-FIFO | Emerging Cross-Sectional Technologies | 0 | Active |
| US7428653B2 | Method and system for execution and latching of data in alternate threads | Physics | 0 | Active |
| US11550750B2 | Memory network processor | Emerging Cross-Sectional Technologies | 0 | Active |
| US11544072B2 | Memory-network processor with programmable optimizations | Emerging Cross-Sectional Technologies | 0 | Active |
| US11327753B2 | Processor instructions to accelerate FEC encoding and decoding | Physics | 0 | Active |
| US11030023B2 | Processing system with interspersed processors DMA-FIFO | Emerging Cross-Sectional Technologies | 0 | Active |
| US10691451B2 | Processor instructions to accelerate FEC encoding and decoding | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.