Peripheral component interconnect (PCI) backplane connectivity system on chip (SoC)

US11030144B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Jason A. T. Jones · Richmond, US
• Sriramakrishnan Govindarajan · Bengaluru, IN
• Mihir Narendra Mody · Kanchinakote, IN
• Kishon Vijay Abraham Israel Vijayponraj · Bengaluru, IN
• Bradley Douglas Cobb · Sugar Land, US
• Sanand Prasad · Plano, US
• Gregory Raymond Shurtz · Houston, US
• Martin Jeffrey Ambrose · Missouri City, US
• Jayant Thakur · Bengaluru, IN

Key dates

• Filing date: Dec 14, 2018
• Grant date: Jun 8, 2021
• Expiry date: Dec 14, 2038

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2213/0026
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

An integrated circuit. The integrated circuit comprises an interconnect communication bus and a plurality of peripheral component interconnect (PCI) multi-function endpoints (MFN-EPs) coupled to the interconnect communication bus, each PCI MFN-EP comprising a multiplexing device, a first address translation unit (ATU), and at least one PCI function circuit, each PCI function circuit comprising another ATU and a plurality of base address registers (BARs).