Integrated circuit with constrained metal line arrangement
US11030382B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Oct 31, 2019 |
| Grant date | Jun 8, 2021 |
| Priority date | — |
| Expiry date | Oct 31, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/975
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes steps of dividing a first arrangement of metal lines in a circuit layout into two sets of metal lines, a first set of metal lines in a peripheral area, and a second set of metal lines in a center area. The arrangement of metal lines is configured to electrically connect to contacts of a second layer of the circuit layout. The method includes adjusting a metal line perimeter of at least one metal line in the center area to make a second arrangement of metal lines, where each adjusted metal line perimeter is separated from contacts in the second layer of the integrated circuit layout by at least a check distance. Metal line material is deposited into a set of openings in a dielectric layer of the integrated circuit, the set of openings corresponding to the second arrangement of metal lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.