XinYong WANG
22Patents
2h-index
36Co-inventors
49Inventor score
Filing activity: Sep 2, 2015 → Mar 25, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10741539B2 | Standard cells and variations thereof within a standard cell library | Physics | 3 | Active |
| US11182529B2 | Semiconductor device including power-grid-adapted route-spacing and method for generating layout diagram of same | Electricity | 2 | Active |
| US9900807B2 | Circuit switched fallback method and device | Electricity | 2 | Active |
| US10339250B2 | Method of generating engineering change order (ECO) layout of base cell and computer-readable medium comprising executable instructions for carrying out said method | Electricity | 2 | Active |
| US11030382B2 | Integrated circuit with constrained metal line arrangement | Electricity | 1 | Active |
| US11748550B2 | Integrated circuit with constrained metal line arrangement | Electricity | 1 | Active |
| US12288786B2 | Shared well structure manufacturing method | Electricity | 0 | Active |
| US12272658B2 | Method of making electrostatic discharge protection cell and antenna integrated with through silicon via | Electricity | 0 | Active |
| US10565345B2 | Semiconductor device having engineering change order (ECO) cells | Electricity | 0 | Active |
| US9894582B2 | Congestion control implementation method and apparatus | Electricity | 0 | Active |
| US10231152B2 | Network handover method, device, and system | Electricity | 0 | Active |
| US11182533B2 | Standard cells and variations thereof within a standard cell library | Physics | 0 | Active |
| US11942441B2 | Electrostatic discharge protection cell and antenna integrated with through silicon via | Electricity | 0 | Active |
| US11030373B2 | System for generating standard cell layout having engineering change order (ECO) cells | Electricity | 0 | Active |
| US11704472B2 | Standard cells and variations thereof within a standard cell library | Physics | 0 | Active |
| US11876088B2 | Shared well structure, layout, and method | Electricity | 0 | Active |
| US12393762B2 | Method for generating a layout diagram of a semiconductor device including power-grid- adapted route-spacing | Electricity | 0 | Active |
| US10212634B2 | Communication method, device, and system | Electricity | 0 | Active |
| US11817350B2 | Method for manufacturing standard cell regions and engineering change order (ECO) cell regions | Electricity | 0 | Active |
| US12271678B2 | Integrated circuit with constrained metal line arrangement, method of using, and system for using | Electricity | 0 | Active |
| US12199037B2 | Standard and engineering change order (ECO) cell regions and semiconductor device including the same | Electricity | 0 | Active |
| US12080658B2 | Integrated circuit device with antenna effect protection circuit and method of manufacturing | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.