Memory circuit capable of implementing calculation operations
US11031076B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2019 |
| Grant date | Jun 8, 2021 |
| Priority date | — |
| Expiry date | Nov 15, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit including: a plurality of elementary storage cells arranged in an array of rows and of columns, the cells of a same column sharing a same read bit line and a same write bit line; an internal control circuit capable of implementing a calculation operation including the simultaneous activation in read mode of at least two rows of the array; and a shuffle circuit including a data input register, a configuration register, and an output port, the shuffle circuit being capable of delivering on its output port the data stored in its input register shuffled according to a shuffle operation defined according to the state of its configuration register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.