Semiconductor package and method of fabricating semiconductor package
US11031371B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2017 |
| Grant date | Jun 8, 2021 |
| Priority date | — |
| Expiry date | Oct 14, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06555
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present technology relates to a semiconductor package. The semiconductor package comprises: a first component comprising a plurality of first dies stacked on top of each other, each of first dies comprising at least one side surface and an electrical contact exposed on the side surface, and the plurality of first dies aligned so that the corresponding side surfaces of all first dies substantially coplanar with respect to each other to form a common sidewall; a first conductive pattern formed over the sidewall and at least partially spaced away from the sidewall, the first conductive pattern electrically interconnecting the electrical contacts of the plurality of first dies; at least one second component; and a second conductive pattern formed on a surface of the second component, the second conductive pattern affixed and electrically connected to the first conductive pattern formed over the sidewall of the first component.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.