Integration of three-dimensional NAND memory devices with multiple functional chips
US11031377B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 24, 2019 |
| Grant date | Jun 8, 2021 |
| Priority date | — |
| Expiry date | Jul 24, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of three-dimensional semiconductor devices and fabrication methods are disclosed. The method includes forming a first and a second memory chips and a microprocessor chip. The method also includes bonding a first interconnect layer of the first memory chip with a second interconnect layer of the second memory chip, such that one or more first memory cells of the first memory chip are electrically connected with one or more second memory cells of the second memory chip through interconnect structures of the first and second interconnect layers. The method further includes bonding a third interconnect layer of the microprocessor chip with a substrate of the second memory chip, such that the one or more microprocessor devices of the microprocessor chip are electrically connected with one or more second memory cell of the second memory chip through interconnect structures of the second and third interconnect layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.