Standard cell for removing routing interference between adjacent pins and device including the same
US11031385B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2019 |
| Grant date | Jun 8, 2021 |
| Priority date | — |
| Expiry date | Dec 23, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/975
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit including a first standard cell including, first transistors, the first transistors being first unfolded transistors, a first metal pin, a second metal pin, and a third metal pin on a first layer, the first metal pin and the second metal pin having a first minimum metal center-to-metal center pitch therebetween less than or equal to 80 nm, a fourth metal pin and a fifth metal pin at a second layer, the fourth metal pin and the fifth metal pin extending in a second direction, the second direction being perpendicular to the first direction, a first via between the first metal pin and the fourth metal pin, and a second via between the third metal pin and the fifth metal pin such that a first via center-to-via center space between the first via and the second via is greater than double the first minimum metal center-to-metal center pitch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.