Peripheral logic circuits under DRAM memory arrays
US11031405B2 · kind B2 · utility
2Cited by
2References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 2, 2017 |
| Grant date | Jun 8, 2021 |
| Priority date | — |
| Expiry date | Nov 2, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1206
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various embodiments comprise methods and related apparatuses formed from those methods for placing at least portions of peripheral circuits under a DRAM memory array, where the peripheral circuits are used to control an operation of the DRAM memory array. In an embodiment, a memory apparatus includes a DRAM memory array and at least one peripheral circuit formed under the DRAM memory array, where the at least one peripheral circuit includes at least one circuit type selected from sense amplifiers and sub-word line drivers. Additional apparatuses and methods are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.