System, apparatus and method for processing remote direct memory access operations with a device-attached memory
US11036650B2 · kind B2 · utility
7Cited by
1References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 19, 2019 |
| Grant date | Jun 15, 2021 |
| Priority date | — |
| Expiry date | Sep 19, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a processor includes: one or more cores to execute instructions; at least one cache memory; and a coherence circuit coupled to the at least one cache memory. The coherence circuit may have a direct memory access circuit to receive a write request, and based at least in part on an address of the write request, to directly send the write request to a device coupled to the processor via a first bus, to cause the device to store data of the write request to a device-attached memory. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.