Inventor · Redmond, WA, US

Ishwar Agarwal

43Patents
4h-index
54Co-inventors
62Inventor score

Filing activity: Sep 26, 2014 → Apr 22, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US11847459B2 Direct swap caching with zero line optimizations Physics 10 Active
US9946676B2 Multichip package link Physics 7 Active
US11036650B2 System, apparatus and method for processing remote direct memory access operations with a device-attached memory Physics 7 Active
US11216396B2 Persistent memory write semantics on PCIe with existing TLP definition Physics 4 Active
US10614000B2 High bandwidth link layer for coherent messages Physics 4 Active
US11201838B2 System, apparatus and method for increasing efficiency of link communications Electricity 4 Active
US11210218B1 Addressing for disaggregated memory pool Physics 3 Active
US10437616B2 Method, apparatus, system for optimized work submission to an accelerator work queue Physics 2 Active
US11204867B2 PCIe controller with extensions to provide coherent memory mapping between accelerator memory and host memory Emerging Cross-Sectional Technologies 2 Active
US10970238B2 Non-posted write transactions for a computer bus Emerging Cross-Sectional Technologies 2 Active
US11481116B2 Computing device with independently coherent nodes Physics 2 Active
US9727475B2 Method and apparatus for distributed snoop filtering Physics 1 Active
US9690706B2 Changing cache ownership in clustered multiprocessor Physics 1 Active
US11366773B2 High bandwidth link layer for coherent messages Physics 1 Active
US11989416B2 Computing device with independently coherent nodes Physics 1 Active
US11321171B1 Memory operations management in computing systems Physics 1 Active
US12242376B2 Paging in thin-provisioned disaggregated memory Physics 0 Active
US11599415B2 Memory tiering techniques in computing systems Physics 0 Active
US11860783B2 Direct swap caching with noisy neighbor mitigation and dynamic address range assignment Physics 0 Active
US11182313B2 System, apparatus and method for memory mirroring in a buffered memory architecture Physics 0 Active
US11347662B2 Method, apparatus, system for early page granular hints from a PCIe device Physics 0 Active
US12300304B2 Detecting and mitigating memory attacks Physics 0 Active
US11726927B2 Method, apparatus, system for early page granular hints from a PCIe device Physics 0 Active
US12182620B2 Systems and methods with integrated memory pooling and direct swap caching Physics 0 Active
US12314174B2 Addressing for disaggregated memory pool Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.