Integrated circuit methods using single-pin imaginary devices
US11036913B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 2, 2020 |
| Grant date | Jun 15, 2021 |
| Priority date | — |
| Expiry date | Mar 2, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes accessing, from a memory, a schematic diagram of a circuit that depicts components of the circuit and, connected to one or more of the components, single-pin imaginary devices associated with group properties of the components. The method further includes automatically generating a design layout for the circuit based on the schematic diagram. The design layout comprises shapes representing the components and, on each shape representing a specific component that is connected to a single-pin imaginary device, a specific group label corresponding to a specific group property of the specific component. Placement of the shapes within the design layout is group label dependent. Accessing of the schematic diagram and the automatically generating of the design layout are performed by a layout generator tool executed by a processor of a computer-aided design system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.