Vikrant Chauhan
14Patents
3h-index
45Co-inventors
52Inventor score
Filing activity: Feb 13, 2012 → Mar 2, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10199270B2 | Multi-directional self-aligned multiple patterning | Electricity | 5 | Active |
| US8856715B1 | Capacitor designs for integrated circuits utilizing self-aligned double patterning (SADP) | Physics | 5 | Active |
| US8932961B2 | Critical dimension and pattern recognition structures for devices manufactured using double patterning techniques | Electricity | 4 | Active |
| US10347543B2 | FDSOI semiconductor device with contact enhancement layer and method of manufacturing | Electricity | 3 | Active |
| US10236350B2 | Method, apparatus and system for a high density middle of line flow | Electricity | 3 | Active |
| US9412655B1 | Forming merged lines in a metallization layer by replacing sacrificial lines with conductive lines | Electricity | 2 | Active |
| US9465907B2 | Multi-polygon constraint decomposition techniques for use in double patterning applications | Physics | 2 | Active |
| US10311186B2 | Three-dimensional pattern risk scoring | Emerging Cross-Sectional Technologies | 0 | Active |
| US10147783B2 | On-chip capacitors with floating islands | Electricity | 0 | Active |
| US10078107B2 | Wafer level electrical test for optical proximity correction and/or etch bias | Physics | 0 | Active |
| US10796973B2 | Test structures connected with the lowest metallization levels in an interconnect structure | Electricity | 0 | Active |
| US10790204B2 | Test structure leveraging the lowest metallization level of an interconnect structure | Electricity | 0 | Active |
| US10579774B2 | Integrated circuit (IC) design systems and methods using single-pin imaginary devices | Physics | 0 | Active |
| US11036913B2 | Integrated circuit methods using single-pin imaginary devices | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.