Row hammer prevention circuit, a memory module including the row hammer prevention circuit, and a memory system including the memory module
US11037618B2 · kind B2 · utility
2Cited by
3References
20Claims
0Family size
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Inventors
Key dates
| Filing date | Apr 24, 2020 |
| Grant date | Jun 15, 2021 |
| Priority date | — |
| Expiry date | Apr 24, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A row hammer prevention circuit for providing a reference address to perform an additional refresh operation includes a history storage circuit configured to store one or more first addresses, each of the first addresses having been provided as the reference address. The row hammer prevention circuit further includes an address storage circuit configured to store a row address corresponding to an active command, a reference address storage circuit configured to store one or more second addresses, and a control circuit configured to provide the reference address in response to a refresh command.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.