Column erasing in non-volatile memory strings
US11037631B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2019 |
| Grant date | Jun 15, 2021 |
| Priority date | — |
| Expiry date | Jan 18, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3427
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Strings of non-volatile memory cells include one or more joint regions adjacent to dummy non-volatile memory cells. During erase operations, different voltage levels are used for different dummy word lines coupled to respective dummy non-volatile memory cells. For example, a selection circuit may set a voltage level of a particular dummy word line to a voltage level greater than a different dummy word line. In another example, the selection circuit may determine a voltage level for a given dummy word line based on a distance between a non-volatile memory cell coupled to the given dummy word line and a selection device included in a string of non-volatile memory cells. Electron holes generated using the dummy word lines during erase operations may neutralize undesired trapped charges in a non-volatile memory string, thereby reducing disparity in erase times for different strings in the non-volatile memory circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.