Multi-tier 3D memory and erase method thereof
US11037632B1 · kind B1 · utility
2Cited by
3References
8Claims
0Family size
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Key dates
| Filing date | Mar 25, 2020 |
| Grant date | Jun 15, 2021 |
| Priority date | — |
| Expiry date | Mar 25, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided is an erase method for a multi-tier three-dimension (3D) memory including a plurality of tiers and a plurality of blocks, each of the tiers including a plurality of word lines. The erase method includes: in erasing a selected block among the plurality of blocks, in a current iteration, selecting at least one tier among the plurality of tiers to be erased by a first erase voltage; determining whether the at least one tier passes erase verification; and if the at least one tier passes erase verification, in a next iteration, inhibiting the at least tier which already passes erase verification from erase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.