Test device and test method of semiconductor storage device
US11037649B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2020 |
| Grant date | Jun 15, 2021 |
| Priority date | — |
| Expiry date | Mar 10, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A test device capable of measuring characteristics of respective transistors constituting a memory cell is provided. The test device for testing a SRAM connects a resistor to a bit line on one side of a memory cell selected by a word line selection circuit and a bit line selection circuit of the SRAM. In a manner that a selected transistor and a resistor of the memory cell constitute a source follower circuit, the test device applies a voltage to each portion of the memory cell, applies an input voltage to a gate of the transistor constituting the source follower circuit, and inputs an output voltage outputted from a source of the transistor constituting the source follower circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.