Spur and quantization noise cancellation for PLLS with non-linear phase detection
US11038521B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2020 |
| Grant date | Jun 15, 2021 |
| Priority date | — |
| Expiry date | Feb 28, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/376
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A fractional-N phase-locked loop (PLL) has a time-to-voltage converter with second order non linearity. The time-to voltage-converter provides an analog error signal indicating a phase difference between the reference clock signal with a period error and a feedback signal supplied by a fractional-N feedback divider. The spur results in quantization noise associated with the fractional-N feedback divider being frequency translated. To address the frequency translated noise, a spur cancellation circuit receives a residue signal indicative of the quantization noise and a spur signal indicative of the spur. The non-linearity of the time-to-voltage converter is mimicked digitally through terms of a polynomial generated to cancel the noise. The generated polynomial is coupled to a delta sigma modulator that controls a digital to analog converter that adds/subtracts a voltage value to/from the error signal to thereby cancel the quantization noise including the frequency translated quantization noise.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.