Optimized scan chain diagnostic pattern generation for reversible scan architecture
US11041906B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 23, 2019 |
| Grant date | Jun 22, 2021 |
| Priority date | — |
| Expiry date | Aug 29, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R35/00
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system and method for performing scan chain testing is disclosed. Scan cells, in the form of scan chains, are inserted into circuit designs for testing those circuit designs. The integrity of the scan chains is checked for defects before testing the circuit under test. In order to do so, various scan chain patterns, including one or both of U-turn and Z-turn patterns, are used in order to generate scan chain test data. The scan chain test data is analyzed in order to identify one or both of a type of defect (e.g., a timing fault, stuck-at fault, etc.) or a location of the defect. Further, the scan chain testing is performed using chain patterns with adaptive length.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.