Providing interrupts from an input-output memory management unit to guest operating systems
US11042495B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Sep 20, 2019 |
| Grant date | Jun 22, 2021 |
| Priority date | — |
| Expiry date | Sep 20, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2009/45579
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic device includes a processor that executes a guest operating system; a memory having a guest portion that is reserved for storing data and information to be accessed by the guest operating system; and an input-output memory management unit (IOMMU). The IOMMU performs operations for signaling an interrupt to the guest operating system. For these operations, the IOMMU acquires, from an entry in an interrupt remapping table associated with the guest operating system, a location in a virtual advanced programmable interrupt controller (APIC) backing page for the guest operating system in the guest portion of the memory. The IOMMU then writes information about the interrupt to the location in the virtual APIC backing page. The IOMMU next communicates an indication of the interrupt to the guest operating system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.