Method of certifying safety levels of semiconductor memories in integrated circuits
US11042688B1 · kind B1 · utility
2Cited by
24References
20Claims
0Family size
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Key dates
| Filing date | Jun 9, 2020 |
| Grant date | Jun 22, 2021 |
| Priority date | — |
| Expiry date | Jun 9, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes specifying a target memory macro with one or more parameters, finding function-blocks in the target memory macro, and determining failure rates of the function-blocks based on an amount of transistors and area distributions in a collection of base cells. The method includes generating a failure-mode analysis for the target memory macro, from a memory compiler, based on the failure rates of the function-blocks. The method includes determining a safety level of the target memory macro, based upon the failure-mode analysis of the target memory macro.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.