High bandwidth destructive read embedded memory
US11043256B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2019 |
| Grant date | Jun 22, 2021 |
| Priority date | — |
| Expiry date | Jun 29, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4097
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described are mechanisms and methods for amortizing the cost of address decode, row-decode and wordline firing across multiple read accesses (instead of just on one read access). Some or all memory locations that share a wordline (WL) may be read, by walking through column multiplexor addresses (instead of just reading out one column multiplexor address per WL fire or memory access). The mechanisms and methods disclosed herein may advantageously enable N distinct memory words to be read out if the array uses an N-to-1 column multiplexor. Since memories such as embedded DRAMs (eDRAMs) may undergo a destructive read, for a given WL fire, a design may be disposed to sense N distinct memory words and restore them in order.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.