Integrated circuit devices with well regions
US11043431B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 22, 2019 |
| Grant date | Jun 22, 2021 |
| Priority date | — |
| Expiry date | Apr 22, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/00
Abstract
A method includes forming a deep well region of a first conductivity type in a substrate, implanting a portion of the deep well region to form a first gate, and implanting the deep well region to form a well region. The well region and the first gate are of a second conductivity type opposite the first conductivity type. An implantation is performed to form a channel region of the first conductivity type over the first gate. A portion of the deep well region overlying the channel region is implanted to form a second gate of the second conductivity type. A source/drain implantation is performed to form a source region and a drain region of the first conductivity type on opposite sides of the second gate. The source and drain regions are connected to the channel region, and overlap the channel region and the first gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.