Low resistivity interconnects with doped barrier layer for integrated circuits
US11043454B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 13, 2019 |
| Grant date | Jun 22, 2021 |
| Priority date | — |
| Expiry date | May 13, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53252
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming an interconnect for an integrated circuit includes: identifying an interconnect barrier material, identifying a plurality of potential dopant elements, creating an ensemble of potential barrier structures including the interconnect barrier material doped at a plurality of doping positions and a plurality of doping amounts for each of the plurality of potential dopant elements, calculating a density of states for each of the barrier structures of the ensemble, selecting a dopant element and a doping amount based on the density of states, and depositing a barrier layer including an alloy, the alloy including the interconnect barrier material and the selected dopant element at the selected doping amount.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.