Semiconductor device and manufacturing method thereof
US11043489B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2018 |
| Grant date | Jun 22, 2021 |
| Priority date | — |
| Expiry date | Jul 30, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
Abstract
A semiconductor device includes a first channel region disposed over a substrate, and a first gate structure disposed over the first channel region. The first gate structure includes a gate dielectric layer disposed over the channel region, a lower conductive gate layer disposed over the gate dielectric layer, a ferroelectric material layer disposed over the lower conductive gate layer, and an upper conductive gate layer disposed over the ferroelectric material layer. The ferroelectric material layer is in direct contact with the gate dielectric layer and the lower gate conductive layer, and has a U-shape cross section.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.