Semiconductor structure and manufacturing method of the same
US11043531B2 · kind B2 · utility
1Cited by
3References
20Claims
0Family size
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Key dates
| Filing date | Nov 20, 2019 |
| Grant date | Jun 22, 2021 |
| Priority date | — |
| Expiry date | Nov 20, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01F10/329
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a semiconductor structure having a memory region. The semiconductor structure includes an Nth metal layer in a memory region and a periphery region, the periphery region spanning a wider area than the memory region, a plurality of magnetic tunneling junctions (MTJs) over the Nth metal layer, the plurality of MTJs having at least one of mixed pitches and mixed sizes, a top electrode via over each of the plurality of MTJs; and an (N+M)th metal layer over the plurality of MTJs. A method for manufacturing the semiconductor structure is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.