Method of fabricating tantalum nitride barrier layer and semiconductor device thereof
US11043573B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Oct 31, 2018 |
| Grant date | Jun 22, 2021 |
| Priority date | — |
| Expiry date | Nov 23, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating tantalum nitride barrier layer in an ultra low threshold voltage semiconductor device is provided. The method includes forming a high-k dielectric layer over a semiconductor substrate. Subsequently, a tantalum nitride barrier layer is formed on the high-k dielectric layer. The tantalum nitride barrier layer has a Ta:N ratio between 1.2 and 3. Next, a plurality of first metal gates is formed on the tantalum nitride barrier layer. The first metal gates are patterned, and then a second metal gate is formed on the tantalum nitride barrier layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.