Systems, methods, and apparatuses for last branch record support compatible with binary translation and speculative execution using an architectural bit array and a write bit array
US11048516B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2015 |
| Grant date | Jun 29, 2021 |
| Priority date | — |
| Expiry date | Aug 15, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30101
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, methods, and apparatuses for last branch record support are described. In an embodiment, a hardware processor core comprises a hardware execution unit to execute a branch instruction, at least two last branch record (LBR) registers to store a source and destination information of a branch taken during program execution, wherein an entry in a LBR register is to include an encoding of the branch, a write bit array to indicate which LBR register is architecturally correct, an architectural bit array to indicate when an LBR register has been written, and a plurality of top of stack pointers to indicate which LBR register in a LBR register stack is to be written.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.