Paul Caprioli
88Patents
13h-index
78Co-inventors
87Inventor score
Filing activity: Jan 21, 2003 → Jun 9, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7930695B2 | Method and apparatus for synchronizing threads on a processor that supports transactional memory | Physics | 72 | Active |
| US8041900B2 | Method and apparatus for improving transactional memory commit latency | Physics | 70 | Active |
| US7617421B2 | Method and apparatus for reporting failure conditions during transactional execution | Physics | 62 | Active |
| US7461208B1 | Circuitry and method for accessing an associative cache with parallel determination of data and data availability | Physics | 58 | Expired |
| US8161273B2 | Method and apparatus for programmatically rewinding a register inside a transaction | Physics | 57 | Active |
| US7421465B1 | Arithmetic early bypass | Physics | 53 | Active |
| US7509481B2 | Patchable and/or programmable pre-decode | Physics | 25 | Expired |
| US7480787B1 | Method and structure for pipelining of SIMD conditional moves | Physics | 24 | Expired |
| US7584346B1 | Method and apparatus for supporting different modes of multi-threaded speculative execution | Physics | 21 | Active |
| US7571304B2 | Generation of multiple checkpoints in a processor that supports speculative execution | Physics | 21 | Expired |
| US7293163B2 | Method and apparatus for dynamically adjusting the aggressiveness of an execute-ahead processor to hide memory latency | Physics | 18 | Expired |
| US7395418B1 | Using a transactional execution mechanism to free up processor resources used by a busy-waiting thread | Physics | 15 | Expired |
| US7293161B1 | Deferring loads and stores when a load buffer or store buffer fills during execute-ahead mode | Physics | 15 | Expired |
| US7707359B2 | Method and apparatus for selectively prefetching based on resource availability | Physics | 13 | Active |
| US9477453B1 | Technologies for shadow stack manipulation for binary translation systems | Physics | 11 | Active |
| US7331039B1 | Method for graphically displaying hardware performance simulators | Emerging Cross-Sectional Technologies | 9 | Expired |
| US8732438B2 | Anti-prefetch instruction | Physics | 9 | Active |
| US9703948B2 | Return-target restrictive return from procedure instructions, processors, methods, and systems | Physics | 8 | Active |
| US7257699B2 | Selective execution of deferred instructions in a processor that supports speculative execution | Physics | 8 | Expired |
| US9417855B2 | Instruction and logic to perform dynamic binary translation | Physics | 8 | Active |
| US7836290B2 | Return address stack recovery in a speculative execution computing apparatus | Physics | 7 | Expired |
| US7353363B2 | Patchable and/or programmable decode using predecode selection | Physics | 5 | Expired |
| US7689813B2 | Method and apparatus for enforcing membar instruction semantics in an execute-ahead processor | Physics | 5 | Expired |
| US10450091B2 | Package acceptance, guidance, and refuel system for drone technology | Performing Operations; Transporting | 5 | Active |
| US8484434B2 | Index generation for cache memories | Physics | 5 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.